Printed circuit board power distribution network modeling, analysis and design, and, statistical crosstalk analysis for high speed digital links

High-speed digital systems are moving to higher data rates and smaller supply voltages as the scale of integration goes smaller. With the smaller bit periods and the smaller operating voltages, the tolerable timing and noise margins are reducing. There are many sources of disturbances contributing to the tolerance margins. These margins have to account for inter symbol interference (ISI), reflections, jitter, noise from power distribution networks (PDN) and crosstalk. An important task during the design phase of the system is to find and mitigate the noise from such sources. This thesis proposes modeling and analysis methodology to resolve some of the problems while proposing relevant design methodologies to reduce the system design cycles. PDN design forms a critical part of a high-speed digital design to provide a low-noise power supply to the integrated circuits (ICs) within some peak voltage ripple for normal functioning. Switching of transistors in the IC leads to a high-frequency current draw and generates the simultaneous switching noise (SSN), which propagates along the PDN from the chip to the PCB and causes several EMI and SI problems. A physics-based modeling approach for PCB PDN is proposed which is used for analysis and design guideline development. A design methodology is developed which guides the designer to make better design decisions, knowing the impact on PDN performance without the use of full-wave tools. Crosstalk forms a critical part of the budget, and if ignored, can lead to design failures. A statistical method to find the distribution of crosstalk at the victim using the single bit response principle is proposed. The methodology is extended to multiple-aggressor system, and, can be used to identify worst case crosstalk and find dominant crosstalk contributors in a system. --Abstract, page iii

The study of a model for via transition and the multi-layer via transition tool GUI design

One of the many challenges faced by engineers working with the present design scenario is to estimate the extent to which a signal, with significant high frequency content, is affected when it is routed on a printed circuit board. The printed circuit board routing will include the transition through the geometries like micro-strip or strip-line transmission lines, via transitions, and irregularities or asymmetries in the aforementioned geometries. One of these discontinuities, the via transition, results in the interaction of the signal on the via and the cavity (plane-pair) through which it passes. The via transition modeling will help characterize a block in the signal path. Section 1 explains the cavity model, and derives an expression for the impedance at a port in a rectangular cavity. The via to cavity connection, and the via capacitance calculation is explained. Then, five practical examples are used to show the model assembly in a circuit fashion, and the results are compared to the measurements. This modeling approach has been automated and integrated into the Multilayer Via Transition Tool, a tool that models all the common PCB geometries and provides the results as network parameters for the user defined ports. This tool is used for performance analysis and design optimization for the high speed PCBs. The tool includes a basic graphic user interface and an engine. Section 2 explains the design methodology for the provided graphic user interface. It explains interface design from the basic set of user inputs required by the engine to run. This section also talks about the difficulties in implementing the interface, and the required improvements for a professional tool --Abstract, page iii

ESD Behavior of RF Switches and Importance of System Efficient ESD Design

RF Switches Are Typically Used in the RF Front-End of Portable Devices Such as Antenna or Matching Tuners to Improve the RF Link Performance. They Are Usually the First Active Devices after the Antenna and Are Vulnerable to Primary or Secondary ESD Discharges to the Antennas. This Paper Investigates the ESD Behavior of One of the High Frequency Switches Used in the RF-Front-End of Portable Devices and Expresses the Importance of the ESD Pulse that Passes through the Switch and Reaches the Next Stage in the RF Path, Possibly Damaging the Next Stage

Design Tips

Welcome to Design Tips! This article will examine how to minimize the inductance associated with mounting decoupling capacitors to power/ground-reference planes. The configuration can have a significant impact on the apparent inductance. The total number of capacitors can be reduced with careful configuration control

Investigation of S21 Magnitude Extraction Methodologies by using a Pattern Generator and Sampling Oscilloscope

S-parameter measurements of a digital link path are measured with VNAs or high-end TDRs. For multi-port in-situ measurements, these become inconvenient and time consuming. However, it can be handled more conveniently in the time domain (TD) by using a pattern generator and a multichannel sampling oscilloscope, which are used for eye-diagram measurements. This paper outlines and compares three methods to extract S21 magnitude from the time domain measurements using a pattern generator and a sampling oscilloscope for any channel. The setup differs in terms of the input waveform and the processing. The comparison provides insight into the advantages and limitations of each method

Equivalent circuit model for power bus design in multi-layer PCBs with via arrays

An equivalent circuit model for multilayer power planes with multiple via arrays is proposed. The complexity of the actual geometry is greatly reduced in the circuit model with the accuracy maintained. The model is corroborated by measurements.close2

Designing Test Patterns for Effective Measurement of Typical TSV Pairs in a Silicon Interposer

In this paper, practical test patterns are designed to calculate the characteristics of Through-Silicon Via (TSV) pairs in a silicon interposer. Proposed test patterns include probing pads, traces and TSVs, which are modeled by a combination of impedances and admittances. Performance of the test patterns is obtained from simulation models built in full wave simulation solver. TSV response is then obtained by de-embedding the pad and trace from the test patterns. The TSV response is also verified by analytical TSV characterization and full wave simulation results for only TSV structures. Thus the paper provides a guide to design feasible test structures from which true response of a TSV pair can be derived

Plane-Pair PEEC Models for PDN using Sub-Meshing

In this paper, we present an improved plane-pair model for power distribution system modeling using the partial element equivalent circuit approach. The modified nodal analysis with a sub-meshing strategy leads to an efficient and accurate circuit solution in both the frequency domain and time domain